The present invention pertains to the field of electronic circuits. More particularly, the present invention relates to the design of flip-flop circuitry.
Flip-flop circuits are used to maintain an output state (Q) based upon the sampling of an input data signal (D) at a particular point in time determined by a clock signal (CLK). The sampling of the input data signal is activated either by the edge or the level of the clock signal. At all other times, the output of the flip-flop circuit will not respond to changes in the input data signal.
Typical flip-flops have shortcomings. One such typical flip-flop is the master-slave flip-flop, which consists of two stages, the master and the slave. To change the output of the master-slave flip-flop, a signal must propagate through both the master and the slave stages. In fast circuits, this delay can pose problems.
Additionally, the number of logic devices used to build both the master and the slave can be large. This large number of devices may consume more power than desirable.
Also, the master-slave flip-flop requires that the data input be present and stable for a given time before the clock activates the sampling for the flip-flop to accurately respond to the data input. This is called the data xe2x80x9csetupxe2x80x9d time. Setup time affects the speed at which a flip-flop may operate. Thus, a setup time may pose a problem.